The present invention relates to a method for planarizing substrates by chemical-mechanical polishing (CMP). The present invention is applicable in manufacturing high speed integrated circuits having submicron design features and high conductivity interconnect structures with improved reliability and increased production throughput.
The escalating requirements for high density performance associated with ultra large scale integration in semiconductor wiring require dramatically increased packing densities of devices on integrated circuits and require the use of high-resolution photography and isotropic plasma etching. In sub-micron technology, the packing density of devices on integrated circuits is strongly dependant upon the integrity of the metal interconnection density. Accordingly, the design rules are increasingly aggressively scaled requiring more levels of metal to effectively interconnect the high density of the devices on the chip.
Conventional semiconductor methodology comprises the formation of stacked vias between the various levels of metal interconnections to achieve high density metal interconnections. It is necessary to form a planar surface due to the need to employ a shallow depth of focus when exposing the photoresist.
Conventional metal plugs in via holes are formed by conformably depositing a metal, such as tungsten (W), completely filling the via holes. The W overburden is then planarized, as by etching back or chemical-mechanical polishing (CMP), to the surface of the insulating layer in which via holes were formed between patterned metal levels, or to the insulating layer in which the contact openings are formed over the devices on the substrate.
In conventional CMP techniques, a wafer carrier assembly is in contact with a polishing pad mounted on a CMP apparatus. The wafers are typically mounted on a carrier or polishing head which provides a controllable pressure urging the wafers against the rotating polishing pad. The pad has a relative movement with respect to the wafer driven by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of each thin semiconductor wafer and the polishing pad while dispersing a polishing slurry containing abrasive particles in a reactive solution to effect both chemical activity and mechanical activity while applying a pressure between the wafer and the polishing pad.
A conventional CMP system is schematically illustrated in FIG. 1 and comprises a wafer carrier 12 which supports wafer 14 against a backing pad 18. Carrier 12 is rotated on a platen 11 to which a polishing pad 17 is attached. A retainer ring 13 is provided to retain the wafer in the carrier so that it does not come off during CMP. A polishing solution can be dispensed through nozzle 15. Additional nozzle 16 can be provided for rinsing with water or other cleaning functions.
A conventional damascene plug filling and CMP technique is dramatically illustrated in FIGS. 2A and 2B, wherein similar reference numerals denote similar features. Adverting to FIG. 2A, a first conductive layer 20 on a partially completed integrated circuit on a substrate (not shown) of, e.g., aluminum, copper or an alloy thereof, is deposited, as by physical vapor deposition (PVD). First conductive layer 20 is then patterned by conventional photolithographic techniques and isotropic plasma etching is conducted to provide a metal interconnection layer for the devices on the substrate. An insulating layer 21, commonly referred to as an interlayer dielectric (ILD), is then deposited over the patterned conductive layer 20. The ILD is typically comprised of silicon oxide and deposited by a low pressure chemical vapor deposition technique. Insulating layer 21 is then planarized, as by CMP.
An opening 22, referred to as a via hole, is then etched in insulating layer 21 to expose the underlying, patterned first conductive layer 20. A barrier layer, e.g., titanium/titanium nitride, also commonly referred to as a glue layer, is conformably deposited over the insulating layer 21 and in the contact opening 22. A metal layer 24, e.g., W, is then deposited on barrier layer 23 and in via hole 22, as by chemical vapor deposition employing tungsten hexafluoride as a gaseous reactant. CMP is then performed to provide a planarized upper surface 25 as shown in FIG. 2B.
There are several disadvantages attendant upon such conventional CMP techniques, particularly when conducting CMP on W, which problems are exacerbated as device geometries plunge into the deep sub-micron range. One such problem encountered is the troublesome filling of alignment marks 31, shown in FIG. 3, formed in insulating layer 30. It was found that during CMP alignment marks 31 become filled with a substance 32 such that the alignment marks are no longer visible during subsequent alignment of the reticle mask employed during exposure of the photoresist in the step-and-repeat tool for patterning the next level of metal.
Another problem stemming front conventional CMP, particularly with W, is schematically illustrated in FIG. 4 wherein residual tungsten 40 remains on the beveled edges of the wafer (substrate) 5 subsequent to CMP. The residual tungsten 40 is vulnerable to peeling and, hence, contaminates the device causing chip defects during subsequent processing.
There exists a need in the semiconductor industry for methodology enabling the planarization of deposited metal to form reliable metal plugs in contacts and vias without interfering with the alignment marks and/or generating a residue on the beveled edges of the wafer substrate.
An aspect of the present invention is a CMP technique for planarizing metals which does not result in obscuring alignment marks or result in generating edge residues, and does not result in wafer coming off the carrier during CMP.
Additional aspects and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination or may be learned from the practice of the present invention. The aspects of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other aspects are implemented in part by a method of a chemical mechanical polishing (CMP) a substrate surface, the method comprising: mounting the substrate in a carrier comprising a retaining ring, the retaining ring comprising a polymer having a mechanical hardness greater than about 85 durometer; and CMP the substrate surface using a polishing pad having a hardness less than about 60 durometer.
Embodiments of the present invention comprise CMP a substrate surface containing W metalization at a CMP removal rate of at least 3000 xc3x85/min. employing a retaining ring comprising ceramics, quartz, polymer or fiber-reinforced polymer, wherein the substrate surface comprises trench alignment marks extending into the substrate that are free of any substantial amounts of carbon-containing debris subsequent to CMP.
Additional aspects of the present invention will become readily apparent to those skilled in this art from the following detailed description wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.